1. Field of the Invention
This invention relates to sampling network analyzers generally, and more particularly to sampling network analyzers for measuring complex voltage, current, voltage and current ratio, phase angle, and power, including measurements of harmonics as well as fundamental Fourier components. Specifically, the present invention is directed to a sampling network analyzer which incorporates a phase-locked loop to permit the operator to establish a prescribed number of samples per measurement, and to effect such measurement so that the sampling of the input signals occurs coherently with one of the input signals (or with an externally-supplied reference signal). In general, synchronization occurs at a frequency that is related to the frequency of the reference signal by a factor that is the ratio of two integers.
2. Description of the Prior Art
U.S. Pat. No. 3,944,940 discloses a clock pulse generating system in which a sequence of reference pulses is phase-locked to a train of read pulses. In this reference, the PLL employs simple digital logic gates for phase error detection.
U.S. Pat. No. 3,982,193 describes a phase-locked loop arrangement for generating a sampling pulse raster.
U.S. Pat. No. 3,344,350 discloses an improved modulation meter incorporating a phase-locked loop for synchronizing a sampler to a frequency offset from a reference oscillator.
U.S. Pat. No. 3,769,602 describes the use of a phase-locked loop for tracking the phase of a periodic input signal having a repetition rate that may assume one of a number of predetermined values, which may differ by orders of magnitude.